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Ordering number : EN*4999
CMOS LSI
LC78855KM
Digital Audio D/A Converter with Built-in Digital Filters
Preliminary Overview
The LC78855KM is a D/A converter with built-in digital filters for use in digital audio products.
Package Dimensions
unit: mm 3091-MFP28
[LC78855KM]
Features
* * * * * * * * * 8x oversampling digital filters Digital de-emphasis (for Fs = 44.1 kHz) Digital attenuation (with serial input) Soft muting (with parallel inputs) Supports double-speed playback. Supports a 384 fs system clock. PWM output Single 5 V power supply Si gate CMOS process
SANYO: MFP28
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Operating temperature Storage temperature Symbol VDD max VIN max VOUT max Topr Tstg Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -30 to +75 -40 to +125 Unit V V V C C
Allowable Operating Ranges at Ta = -30 to +75C
Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions min 4.5 0 typ 5.0 max 5.5 VDD Unit V V
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
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93098HA (OT) / 83194TH (OT) No. 4999-1/9
LC78855KM DC Characteristics at Ta = -30 to +75C, VDD = 4.5 to 5.5 V, VSS = 0 V
Parameter Input high level voltage (1) Input low level voltage (2) Input high level voltage (1) Input low level voltage (2) Output high level voltage Output low level voltage Allowable power dissipation Symbol VIH1 VIL1 VIH2 VIL2 VOH VOL Pd The XIN pin The XIN pin Pins other than the XIN pin Pins other than the XIN pin IOH = -1 A IOL = 1 A VDD = 5.0 V 175 VDD - 0.1 0.1 250 2.2 0.8 Conditions Ratings min 0.7 VDD 0.3 VDD typ max Unit V V V V V V mW
AC Characteristics at Ta = -30 to +75C, VDD = 4.5 to 5.5 V, VSS = 0 V
Parameter Oscillator frequency BCLK frequency BCLK pulse width Data setup time Data hold time LRCK setup time LRCK hold time CNT1 pulse period CNT1 pulse width CNT2 pulse width Symbol fX fBCX tWB tDS tDH tLS tLH tSHIFT tWS tWL 100 20 20 50 50 1000 300 300 Conditions Ratings min typ 16.9 max 18.5 2.4 Unit MHz MHz ns ns ns ns ns ns ns ns
Timing Diagrams
No. 4999-2/9
LC78855KM Analog Characteristics at Ta = 25C, VDD = 5.0 V
Parameter Total harmonic distortion Signal-to-noise ratio Crosstalk Full-scale output level Dynamic range Symbol THD + N S/N CT VFS DR 1 kHz, 0 dB JIS-A 1 kHz, 0 dB * JIS-A 83 93 80 1.7 Conditions Ratings min typ max 0.01 Unit % dB dB Vrms dB
Note: * For a 1 kHz, 0 dB input, measured in the circuit presented as a sample application circuit.
Block Diagram
Pin Assignment
No. 4999-3/9
LC78855KM Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function RESETB CNT1 CNT2 CNT3 BCLK LRCK DATA MODE CLKOUT XVDD XIN XOUT XGND DGND MUTERO TEST AVDD4 OUTRA AGND2 OUTRB AVDD3 AVDD2 OUTLB AGND1 OUTLA AVDD1 MUTELO DVDD Description Reset input (Internal circuits are initialized when a low level is input to this pin.) When MODE = low: Control data shift clock When MODE = high: Emphasis on/off switch When MODE = low: Control data latch signal input When MODE = high: Standard speed/double speed switch When MODE = low: Control data input When MODE = high: Soft muting input Bit clock input LR clock input Digital audio data input Serial/parallel input setting Clock output Oscillator amplifier power supply Oscillator amplifier input Oscillator amplifier output Oscillator amplifier ground Digital system ground Right channel muting signal output Test pin (Must be tied low in normal operation.) Analog system power supply Right channel output A Analog system ground Right channel output B Analog system ground Analog system ground Left channel output B Analog system ground Left channel output A Analog system ground Left channel muting signal output Digital system power supply
LC78855KM Operation The LC78855KM consists of two major sections; a digital filter block and a D/A converter. 1. Digital Filter Block * Standard speed operation The LC78855KM implements 8x oversampling using three filters: a 43rd order FIR filter, an 11th order FIR filter and a third order FIR filter. De-emphasis is performed using a first order IIR filter.
* Double speed operation This mode is used, for example, for dubbing a CD to a cassette at double speed. The XIN pin functions in the same manner as in standard mode, but the BCLK, LRCK and DATA signals are input at twice the speed. After deemphasis is performed with a first order IIR filter 4x oversampling is performed using two filters: a 43rd order FIR filter and a third order FIR filter.
No. 4999-4/9
LC78855KM 2. 1-Bit D/A Converter Block The 1-bit D/A converter block takes the 8 Fs data input and outputs it as a 384 Fs 1-bit data series.
Input Settings 1. Input data format
2. Mode setting * Serial input mode (MODE = low) Attenuation data, de-emphasis on/off and the standard speed/double speed settings are input to the three lines CNT1, CNT2 and CNT3.
* Parallel input mode (MODE = high) CNT1 functions as emphasis on/off. CNT2 functions as the standard/double speed switch. CNT3 functions as the soft muting on/off switch. -- Standard speed/double speed settings
Mode Serial input mode Parallel input mode Input signal ND CNT2 Low Standard speed Standard speed High Double speed Double speed
-- De-emphasis settings
Mode Serial input mode Parallel input mode Input signal EMP CNT1 Low Off Off High On On
De-emphasis supports an Fs of 44.1 kHz.
No. 4999-5/9
LC78855KM -- Attenuation data settings (serial input mode) When D7 is low: Bits D0 to D6 are input as attenuation data. When D7 is high: Bits D0 to D6 are not input and no attenuation data transformation is performed. The table below shows the relationship between the attenuation data and the output.
Attenuation data 7F (HEX) 7E (HEX) * * * 01 (HEX) 00 (HEX) Audio output (dB) 0 -0.137 * * * -42.144 -
The attenuation for the values 01 to 7E (hexadecimal) is given by the following formula. Attenuation = 20 * log(input data/128) (dB) The digital attenuation interval shifts with a slope of 1024/Fs (s) from 0 to - (dB). If new data is input during a transition, the value begins to change towards the new value at that time. -- Soft muting switch (parallel input mode) Soft muting can be applied by switching the value input to pin CNT3. When CNT3 is high, soft muting will be applied. Soft muting shifts the amplitude from 0 to - (dB) at 1024/Fs (s). 3. Initialization The LC78855KM requires initialization when power is first applied and when the system clock is switched. A reset can be effected by setting the RESETB pin to the low level. The time that low level is held must be at least the time necessary for the power supply voltage to stabilize, the XIN, BCLK and LRCK signals to be applied and for LRCK to complete at least one cycle as shown in the figure below. When RESETB is low, all digital outputs and the internal noise shaper go to zero and the D/A converter outputs an analog zero.
No. 4999-6/9
LC78855KM LC78855KM Outputs 1. CLKOUT This pin outputs a clock with the same frequency as the signal input to XIN. 2. MUTELO, MUTERO These signals output a high level if the attenuation coefficient goes to zero or if the data in each channel has been zero for 213 or more times in a row. 3. OUTLA, OUTLB, OUTRA, OUTRB The LC78855KM data output is output from these four pins in synchronization with the XIN clock. High precision analog signals can be acquired by passing these outputs through differential amplifiers and a low-pass filter. The figure below shows the details of this circuit structure. Sample Output Block Structure
No. 4999-7/9
LC78855KM Filter Characteristics
No. 4999-8/9
LC78855KM Sample Application Circuit
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of September, 1998. Specifications and information herein are subject to change without notice. PS No. 4999-9/9

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